No Clock SVA (Asynchronous events)

All the time temporal and concurrency have hard association with system verilog properties and thus with System Verilog Assertions (SVA). Now the question is how is one suppose to check for asynchronous events using system verilog.

Here is a quick example with is self explanatory.

event start_ev, stop_ev;
parameter LAPSED_TIME = 50;

property no_clock;
   time start_t, end_t;
   @start_ev(1'b1, start_t = $time)|=>
   @stop_ev(1'b1, stop_t = $time) ##0
   (stop_t - start_t <= LAPSED_TIME);
endproperty: no_clock

async_check:assert property (no_clock);

In the above property there is no clock but we use asynchronous start and stop events instead as clocks.